N. Bhavanishankar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
1996–1996
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1996 | ICCD | A VLSI array architecture with dynamic frequency clocking. | N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar |
| 1996 | ICIP | DFLAP: a dynamic frequency linear array processor. | Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar |
| 1996 | ICPR | A dynamic frequency linear array processor for image processing. | N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan |