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N. S. Nagaraj

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

3

Active years

1992–2009

Best venue rank

A*

Where they publish

Papers

18 indexed papers, newest first.

YearVenueTitleAuthors
2009DACMoore's Law: another casualty of the financial meltdown?Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork
2008DACDFM in practice: hit or hype?Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh
2006VLSIDInterconnect Process Variations: Theory and Practice.N. S. Nagaraj
2006VLSIDSmartExtract: Accurate Capacitance Extraction for SOC Designs.Usha Narasimha, Anthony M. Hill, N. S. Nagaraj
2005DACBEOL variability and impact on RC extraction.N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill
2005VLSIDThe Impact of Inductance on Transients Affecting Gate Oxide Reliability.N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell
2004VLSIDA 800 MHz System-on-Chip for Wireless Infrastructure Applications.Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich
2004VLSIDInterconnect Modeling for Copper/Low-k Technologies.N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
2002VLSIDEmbedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification.N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell
2000DACWhen bad things happen to good chips (panel session).N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
2000VLSIDA Practical Approach to Crosstalk Noise Verification of Static CMOS Designs.N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das
1998DACA Practical Approach to Static Signal Electromigration Analysis.N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young
1998DACTaming Noise in Deep Submicron Digital Integrated Circuits (Panel).N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone
1994ISCASApproximate Computation of Signal Characteristics of On-chip RC Interconnect Trees.N. S. Nagaraj, Paul Krivacek, Mark Harward
1993DACA New Optimizer for Performance Optimization of Analog Integrated Circuits.N. S. Nagaraj
1993ISCASA New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing.N. S. Nagaraj
1992VLSIDOPSYN - OASYS Based Pseudosynthesis Tool.N. S. Nagaraj
1992VLSIDWCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits.S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand