Nadine Azmard
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
1995–2007
Best venue rank
A
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | DATE | Temperature and voltage aware timing analysis: application to voltage drops. | B. Lasbouygues, Robin Wilson, Nadine Azmard, Philippe Maurine |
| 2006 | ISCAS | Circuit sizing method under delay constraint. | Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azmard |
| 2005 | DATE | Low Power Oriented CMOS Circuit Optimization Protocol. | Alexandre Verle, Xavier Michel, Nadine Azmard, Philippe Maurine, Daniel Auvergne |
| 2004 | ISCAS | Delay bound based CMOS gate sizing technique. | Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azmard, Daniel Auvergne |
| 2001 | ISCAS | Delay bound determination for timing closure satisfaction. | Nadine Azmard, M. Aline, Daniel Auvergne |
| 1996 | DATE | Design and selection of buffers for minimum power-delay product. | S. Turgis, Nadine Azmard, Daniel Auvergne |
| 1995 | ISLPED | Explicit evaluation of short circuit power dissipation for CMOS logic structures. | S. Turgis, Nadine Azmard, Daniel Auvergne |