Nalesh Sivanandan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2013–2019
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | VLSID | UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. | S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan |
| 2016 | VLSID | RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. | Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan |
| 2015 | HPCC | Compiling HPC Kernels for the REDEFINE CGRA. | Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan |
| 2015 | VLSID | Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. | Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan |
| 2013 | ISCAS | High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. | S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan |