Nanditha P. Rao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2015–2022
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | DSD | An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. | Veerendra S. Devaraddi, Nanditha P. Rao |
| 2022 | ISCAS | An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. | Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie |
| 2021 | DSD | Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. | Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao |
| 2015 | DSD | A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. | Nanditha P. Rao, Madhav P. Desai |