Narender Hanchate
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2004–2006
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | VLSID | A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. | Narender Hanchate, Nagarajan Ranganathan |
| 2004 | VLSID | A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. | Narender Hanchate, Nagarajan Ranganathan |