Natesan Venkateswaran
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
1996–2016
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | DAC | A distributed timing analysis framework for large designs. | Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran |
| 2016 | VLSID | Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. | Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma |
| 2012 | DAC | Reversible statistical | Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov |
| 2012 | DAC | Timing analysis with nonseparable statistical and deterministic variations. | Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran |
| 2006 | DAC | Criticality computation in parameterized statistical timing. | Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah |
| 2005 | ICCAD | Gate sizing using incremental parameterized statistical timing analysis. | Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov |
| 1998 | ICCD | Clock-skew constrained placement for row based designs. | Natesan Venkateswaran, Dinesh Bhatia |
| 1997 | ASPDAC | A constructive method for data path area estimation during high-level VLSI synthesis. | Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri |
| 1996 | VLSID | Clock-Skew Constrained Cell Placement. | Natesan Venkateswaran, Dinesh Bhatia |