Naveen Muralimanohar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
28
Venues
12
Active years
2005–2016
Best venue rank
A*
Where they publish
Papers
28 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ICCD | Enabling technologies for memory compression: Metadata, mapping, and prediction. | Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber |
| 2016 | ISCA | ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. | Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar |
| 2015 | HPCA | Overcoming the challenges of crossbar resistive memory architectures. | Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie |
| 2015 | ICCD | Improving memristor memory with sneak current sharing. | Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon |
| 2015 | ICS | History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. | Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi |
| 2013 | DAC | Understanding the trade-offs in multi-level cell ReRAM memory design. | Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2013 | ICCAD | Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. | Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2012 | DATE | CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. | Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi |
| 2012 | HPCA | Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. | Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
| 2012 | ICCAD | CACTI-IO: CACTI with off-chip power-area-timing models. | Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas |
| 2012 | ISCA | LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. | Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
| 2012 | ISCA | BOOM: Enabling mobile memory based low-power server DIMMs. | Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan |
| 2012 | ISLPED | Design trade-offs for high density cross-point resistive memory. | Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie |
| 2011 | HPCA | FREE-p: Protecting non-volatile memory against both hard and soft errors. | Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez |
| 2011 | ISCA | The role of optics in future high radix switch design. | Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn |
| 2011 | ISCA | Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. | Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
| 2011 | SC | System implications of memory reliability in exascale computing. | Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi |
| 2010 | HPCA | Towards scalable, energy-efficient, bus-based on-chip networks. | Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian |
| 2010 | ISCA | Rethinking DRAM design and organization for energy-constrained multi-cores. | Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
| 2010 | SC | Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. | Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi |
| 2009 | HiPC | Non-uniform power access in large caches with low-swing wires. | Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian |
| 2009 | HPCA | Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. | Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell |
| 2009 | SC | Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. | Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie |
| 2007 | ISCA | Interconnect design considerations for large NUCA caches. | Naveen Muralimanohar, Rajeev Balasubramonian |
| 2007 | MICRO | Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. | Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi |
| 2006 | ISCA | Interconnect-Aware Coherence Protocols for Chip Multiprocessors. | Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter |
| 2006 | ISPASS | Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. | Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian |
| 2005 | HPCA | Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. | Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy |