Nobuhiro Tomabechi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1989–2005
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ISCAS | VLSI architecture based on packet data transfer scheme and its application. | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi |
| 2000 | ISCAS | Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. | Nobuhiro Tomabechi, Teruki Ito |
| 1989 | ICCD | Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. | Nobuhiro Tomabechi |