| 2007 | ICCD | Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. | Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi |
| 2006 | ASPDAC | A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. | Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi |
| 2006 | ICCAD | Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. | Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi |
| 2005 | DAC | Template-driven parasitic-aware optimization of analog integrated circuit layouts. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi |
| 2005 | VLSID | Automatic Device Layout Generation for Analog Layout Retargeting. | Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi |
| 2004 | ASPDAC | Hierarchical extraction and verification of symmetry constraints for analog layout automation. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi |
| 2004 | ASPDAC | Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi |
| 2004 | DAC | Correct-by-construction layout-centric retargeting of large analog designs. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi |
| 2003 | ISCAS | Automatic analog layout retargeting for new processes and device sizes. | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi |