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Odysseas Zografos

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

5

Active years

2014–2025

Best venue rank

A*

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2025ICCADHalf-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node.Halil Kkner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jrgen Bmmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert
2024DACGNN-assisted Back-side Clock Routing Methodology for Advance Technologies.Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto Garca Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
2022DATEDesign enablement of CFET devices for sub-2nm CMOS nodes.Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert
2020DATEMultiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
2018ICCADMajority logic synthesis.Luca G. Amar, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
2017DATEWave pipelining for majority-based beyond-CMOS technologies.Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amar, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
2014DSDMajority Logic Synthesis for Spin Wave Technology.Odysseas Zografos, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
2014ISCASNovel grid-based power routing scheme for regular controllable-polarity FET arrangements.Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli