Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node.

Halil Kkner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jrgen Bmmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert

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