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Oliver Schrape

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

4

Active years

2015–2022

Best venue rank

C

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2022VTCUltra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS.Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, Jess Gutirrez, Milos Krstic, Eckhard Grass, Rolf Kraemer
2020DSDA Glitch-free Clock Multiplexer for Non-Continuously Running Clocks.Steffen Zeidler, Oliver Schrape, Anselm Breitenreiter, Milos Krstic
2020DSDDesign of Radiation Hardened RADFET Readout System for Space Applications.Marko S. Andjelkovic, Aleksandar Simevski, Junchao Chen, Oliver Schrape, Zoran Stamenkovic, Milos Krstic, Stefan D. Ilic, Luka Spahic, Laza Kostic, Goran S. Ristic, Aleksandar Jaksic, Alberto J. Palma, Antonio M. Lallena, Miguel ngel Carvajal
2020DSDDesign Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic
2020IOLTSPISA: Power-robust Multiprocessor Design for Space Applications.Aleksandar Simevski, Oliver Schrape, Carlos Benito, Milos Krstic, Marko S. Andjelkovic
2019DSDAspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops.Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler, Milos Krstic
2019IOLTSSelective Fault Tolerance by Counting Gates with Controlling Value.Anselm Breitenreiter, Stefan Weidling, Oliver Schrape, Steffen Zeidler, Pedro Reviriego, Milos Krstic
2018DDECSFlip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic
2018DSDD-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop.Oliver Schrape, Anselm Breitenreiter, Marko S. Andjelkovic, Milos Krstic
2017DDECSRouting approach for digital, differential bipolar designs using virtual fat-wire boundary pins.Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic
2016DDECSImplementation of DBFN processor for Synthetic Aperture Radar application.Oliver Schrape, Arkadiusz Koczor, Piotr Penkala, Vladimir Petrovic, Milos Krstic
2015DDECSA Design Preconditioning Flow for Low-Noise Circuits.Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic