P. Sai Phaneendra
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2011–2014
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | VLSID | An Optimized Design of Reversible Quantum Comparator. | P. Sai Phaneendra, Chetan Kumar Vudadha, Sreehari Veeramachaneni, M. B. Srinivas |
| 2012 | VLSID | Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. | Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |
| 2011 | DSD | A Unified Architecture for BCD and Binary Adder/Subtractor. | Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |