| 2018 | ASPDAC | Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. | Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2017 | ISCAS | Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. | Rui Liu, Pai-Yu Chen, Shimeng Yu |
| 2016 | DATE | MNSIM: Simulation platform for memristor-based neuromorphic computing system. | Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang |
| 2016 | ICCAD | Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. | Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2016 | ISCAS | Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. | Pai-Yu Chen, Shimeng Yu |
| 2016 | ISCAS | Design of a reliable RRAM-based PUF for compact hardware security primitives. | Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti |
| 2015 | DATE | Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. | Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | ICCAD | Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. | Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | ISCAS | Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. | Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu |
| 2014 | ICCAD | Architecting 3D vertical resistive memory for next-generation storage systems. | Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie |