Pallavi Paliwal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2012–2022
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ISCAS | A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. | Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta |
| 2019 | ISCAS | A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector. | Arun Goyal, Souvik Ghosh, Sandeep Goyal, Pallavi Paliwal, Shalabh Gupta |
| 2016 | VLSID | A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. | Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta |
| 2012 | VLSID | Circuit Optimization at 22nm Technology Node. | Angada B. Sachid, Pallavi Paliwal, S. Joshi, Maryam Shojaei Baghini, Dinesh Sharma, V. Ramgopal Rao |