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Paul T. Hulina

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

6

Active years

1970–1999

Best venue rank

A*

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
1999ICCDEvaluation of Computing in Memory Architectures for Digital Image Processing Applications.David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor
1999RSPA Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems.Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian
1999RSPLanguage-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use.David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor
1995HPCAProgram Balance and Its Impact on High Performance RISC Architectures.Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
1994ICPPStructured Data Access Mechanisms for a Decoupled Computer Architecture.Ali Berrached, Paul T. Hulina, Lee D. Coraor
1994ICPPModule Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories.Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor
1992ISCAMemory Latency Effects in Decoupled Architectures With a Single Data Memory Module.Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor
1991ICPPPerformance Analysis of an Address Generation Coprocessor.Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun
1991ISCAClassification and Performance Evaluation of Instruction Buffering Techniques.Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai
1987ICPPA Hardware Memory Mapping Unit for Efficient Address Computation.Paul T. Hulina, Lee D. Coraor
1985ICPPA Reconfigurable Multiprocessor.Lee D. Coraor, Paul T. Hulina
1970FOCSElimination of Static and Dynamic Hazards in Combinatorial Switching CircuitsJon G. Bredeson, Paul T. Hulina