Pedro P. Carballo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2004–2023
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | DSD | MPSoC FPGA Implementation of Algorithms of Machine Learning for Clinical Applications Using High-Level Design Methodology. | Mario Guanche-Hernndez, Raquel Len, Pedro P. Carballo |
| 2013 | DSD | Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology. | Pedro P. Carballo, Omar Espino, Romn Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Nez |
| 2006 | DSD | VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. | Armando Snchez-Pea, Pedro P. Carballo, Luz Garca, Antonio Nez |
| 2004 | DSD | CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip. | Vctor Reyes, Toms Bautista, Gustavo Marrero Callic, Pedro P. Carballo, Wido Kruijtzer |