| 2026 | FCCM | DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration. | Xingzhen Chen, Zhuoping Yang, Jinming Zhuang, Shixin Ji, Sarah Schultz, Zheng Dong, Weisong Shi, Peipei Zhou |
| 2025 | FCCM | Ph.D. Project AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP. | Zhuoping Yang, Peipei Zhou |
| 2025 | FCCM | Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices. | Jinming Zhuang, Peipei Zhou |
| 2025 | FPGA | Towards Accelerator Customization in Real-time Safety-critical Systems. | Shixin Ji, Xingzhen Chen, Wei Zhang, Zhuoping Yang, Jinming Zhuang, Sarah Schultz, Yukai Song, Jingtong Hu, Alex K. Jones, Zheng Dong, Peipei Zhou |
| 2025 | FPGA | ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. | Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou |
| 2025 | SC | AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. | Zhuoping Yang, Jinming Zhuang, Xingzhen Chen, Alex K. Jones, Peipei Zhou |
| 2025 | RTSS | DERCA: DetERministic Cycle-Level Accelerator on Reconfigurable Platforms in DNN-Enabled Real-Time Safety-Critical Systems. | Shixin Ji, Zhuoping Yang, Xingzhen Chen, Wei Zhang, Jinming Zhuang, Alex K. Jones, Zheng Dong, Peipei Zhou |
| 2024 | ASPDAC | Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets. | Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang, Weifeng Zhang, Dharmesh Jani, Peipei Zhou |
| 2024 | DAC | Enabling On-Device Large Language Model Personalization with Self-Supervised Data Selection and Synthesis. | Ruiyang Qin, Jun Xia, Zhenge Jia, Meng Jiang, Ahmed Abbasi, Peipei Zhou, Jingtong Hu, Yiyu Shi |
| 2024 | FPGA | SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. | Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou |
| 2023 | DAC | High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives. | Jinming Zhuang, Zhuoping Yang, Peipei Zhou |
| 2023 | FPGA | CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. | Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou |
| 2023 | ICCAD | AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP. | Zhuoping Yang, Jinming Zhuang, Jiaqi Yin, Cunxi Yu, Alex K. Jones, Peipei Zhou |
| 2022 | DAC | H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. | Xinyi Zhang, Cong Hao, Peipei Zhou, Alex K. Jones, Jingtong Hu |
| 2021 | FPGA | MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. | Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong |
| 2020 | FCCM | Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. | Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong |
| 2018 | FCCM | Latte: Locality Aware Transformation for High-Level Synthesis. | Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou |
| 2018 | FCCM | ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. | Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, Jason Cong |
| 2018 | FPGA | An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). | Yuze Chi, Peipei Zhou, Jason Cong |
| 2018 | ICCAD | SODA: stencil with optimized dataflow architecture. | Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou |
| 2018 | ISPASS | Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework. | Peipei Zhou, Zhenyuan Ruan, Zhenman Fang, Megan Shand, David Roazen, Jason Cong |
| 2017 | DAC | Bandwidth Optimization Through On-Chip Memory Restructuring for HLS. | Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou |
| 2017 | IECON | Lag synchronization for neural networks with mixed delays via adaptive intermittent control. | Peipei Zhou, Shuiming Cai |
| 2017 | SEKE | A Data Filtering Method Based on Agglomerative Clustering. | Xiao Yu, Peipei Zhou, Jiansheng Zhang, Jin Liu |
| 2016 | FCCM | Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. | Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, Andr DeHon |
| 2016 | FPGA | ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). | Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou |
| 2016 | ICCAD | Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. | Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong |
| 2014 | FCCM | A Fully Pipelined and Dynamically Composable Architecture of CGRA. | Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao, Peipei Zhou |