| 2025 | EuroPar | BATCH-DNN: Adaptive and Dynamic Batching for Multi-DNN Accelerators. | Piyumal Ranawaka, Per Stenstrm |
| 2025 | SC | ASaP: Automatic Software Prefetching for Sparse Tensor Computations in MLIR. | Konstantinos Sotiropoulos, Jonas Skeppstedt, Per Stenstrm |
| 2024 | ICS | HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory. | Qi Shao, Angelos Arelakis, Per Stenstrm |
| 2022 | HPCA | GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases. | Alexandra Angerd, Angelos Arelakis, Vasilis Spiliopoulos, Erik Sintorn, Per Stenstrm |
| 2020 | ICPP | A GPU Register File using Static Data Compression. | Alexandra Angerd, Erik Sintorn, Per Stenstrm |
| 2019 | ICPP | SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems. | Muhammad Waqar Azhar, Miquel Perics, Per Stenstrm |
| 2018 | HPCA | ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. | Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenstrm |
| 2017 | RTAS | Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications. | Petros Voudouris, Per Stenstrm, Risat Pathan |
| 2016 | DATE | EUROSERVER: Share-anything scale-out micro-server design. | Manolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Mats, Antimo Bruno, Per Stenstrm, Jrme Martin, Yves Durand, Isabelle Dor |
| 2016 | HPCA | RADAR: Runtime-assisted dead region management for last-level caches. | Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Perics, Per Stenstrm |
| 2016 | RTSS | Timing-anomaly free dynamic scheduling of task-based parallel applications. | Petros Voudouris, Per Stenstrm, Risat Pathan |
| 2015 | ICPP | Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers. | Jochen Hollmann, J. Rubn Titos Gil, Per Stenstrm |
| 2015 | MICRO | HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. | Angelos Arelakis, Fredrik Dahlgren, Per Stenstrm |
| 2014 | DATE | Effective resource management towards efficient computing. | Per Stenstrm |
| 2014 | ICPP | Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory. | Dmitry Knyaginin, Georgi Gaydadjiev, Per Stenstrm |
| 2014 | ISCA | SC | Angelos Arelakis, Per Stenstrm |
| 2014 | RTAS | Overhead-aware temporal partitioning on multicore processors. | Risat Mahmud Pathan, Per Stenstrm, Lars-Goran Green, Torbjorn Hult, Patrik Sandin |
| 2013 | CGO | Improving data access efficiency by using a tagless access buffer (TAB). | Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Sjlander, Per Larsson-Edefors, Sally A. McKee, Per Stenstrm |
| 2013 | HiPC | HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. | Adri Armejach, Anurag Negi, Adrin Cristal, Osman S. Unsal, Per Stenstrm, Tim Harris |
| 2013 | ICPP | Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. | Madhavan Manivannan, Anurag Negi, Per Stenstrm |
| 2012 | HPCA | π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. | Anurag Negi, J. Rubn Titos Gil, Manuel E. Acacio, Jos M. Garca, Per Stenstrm |
| 2012 | SC | Critical lock analysis: diagnosing critical section bottlenecks in multithreaded applications. | Guancheng Chen, Per Stenstrm |
| 2011 | CASES | A unified approach to eliminate memory accesses early. | Mafijul Md. Islam, Per Stenstrm |
| 2011 | ICPP | Implications of Merging Phases on Scalability of Multi-core Architectures. | Madhavan Manivannan, Ben H. H. Juurlink, Per Stenstrm |
| 2011 | ICPP | Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. | Anurag Negi, J. Rubn Titos Gil, Manuel E. Acacio, Jos M. Garca, Per Stenstrm |
| 2011 | ICS | ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. | J. Rubn Titos Gil, Anurag Negi, Manuel E. Acacio, Jos M. Garca, Per Stenstrm |
| 2011 | ICS | Poster: implications of merging phases on scalability of multi-core architectures. | Madhavan Manivannan, Ben H. H. Juurlink, Per Stenstrm |
| 2011 | SBAC-PAD | Classification and Elimination of Conflicts in Hardware Transactional Memory Systems. | Mridha-Mohammad Waliullah, Per Stenstrm |
| 2010 | CASES | Characterization and exploitation of narrow-width loads: the narrow-width cache approach. | Mafijul Md. Islam, Per Stenstrm |
| 2009 | ICS | Cancellation of loads that return zero using zero-value caches. | Md. Mafijul Islam, Sally A. McKee, Per Stenstrm |
| 2008 | DSD | Leveraging Data Promotion for Low Power D-NUCA Caches. | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenstrm |
| 2008 | ICPP | Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. | Martin Thuresson, Per Stenstrm |
| 2007 | DATE | Microprocessors in the era of terascale integration. | Shekhar Borkar, Norman P. Jouppi, Per Stenstrm |
| 2007 | EuroPar | Starvation-Free Transactional Memory-System Protocols. | M. M. Waliullah, Per Stenstrm |
| 2007 | HPCA | An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. | Haakon Dybdahl, Per Stenstrm |
| 2007 | ICPP | Loop-level Speculative Parallelism in Embedded Applications. | Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenstrm |
| 2006 | HiPC | A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. | Haakon Dybdahl, Per Stenstrm, Lasse Natvig |
| 2006 | HPCA | Chip-multiprocessing and beyond. | Per Stenstrm |
| 2006 | SBAC-PAD | Scalable Value-Cache Based Compression Schemes for Multiprocessors. | Martin Thuresson, Per Stenstrm |
| 2006 | SBAC-PAD | Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. | Fredrik Warg, Per Stenstrm |
| 2005 | ISCA | A Robust Main-Memory Compression Scheme. | Magnus Ekman, Per Stenstrm |
| 2005 | ISPASS | Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. | Magnus Ekman, Per Stenstrm |
| 2003 | HiPC | One Chip, One Server: How Do We Exploit Its Power? | Per Stenstrm |
| 2003 | ICPP | Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. | Magnus Ekman, Per Stenstrm |
| 2003 | ICPP | A Novel Approach to Cache Block Reuse Predictions. | Jonas Jalminger, Per Stenstrm |
| 2003 | ISPASS | Integrating complete-system and user-level performance/power simulators: the SimWattch approach. | Jianwei Chen, Michel Dubois, Per Stenstrm |
| 2002 | HPCA | The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. | Martin Kmpe, Per Stenstrm, Michel Dubois |
| 2002 | ISLPED | TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. | Magnus Ekman, Per Stenstrm, Fredrik Dahlgren |
| 2001 | EuroPar | A Case Study of Load Distribution in Parallel View Frustum Culling and Collision Detection. | Ulf Assarsson, Per Stenstrm |
| 2000 | EuroPar | Parallel Computer Architecture. | Silvia M. Mller, Per Stenstrm, Mateo Valero, Stamatis Vassiliadis |
| 2000 | HPCA | A Prefetching Technique for Irregular Accesses to Linked Data Structures. | Magnus Karlsson, Fredrik Dahlgren, Per Stenstrm |
| 2000 | ISCA | Recency-based TLB preloading. | Ashley Saulsbury, Fredrik Dahlgren, Per Stenstrm |
| 2000 | SIGMETRICS | An analytical model of the working-set sizes in decision-support systems. | Magnus Karlsson, Per Stenstrm |
| 1999 | RTSS | Timing Anomalies in Dynamically Scheduled Microprocessors. | Thomas Lundqvist, Per Stenstrm |
| 1999 | RTCSA | A Method to Improve the Estimated Worst-Case Performance of Data Caching. | Thomas Lundqvist, Per Stenstrm |
| 1998 | USENIX | SimICS/Sun4m: A Virtual Workstation. | Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenstrm, Fredrik Lundholm, Magnus Karlsson, Fredrik Dahlgren, Hkan Grahn |
| 1998 | WCAE | A holistic approach to computer system design education based on system simulation techniques. | Per Stenstrm, Fredrik Dahlgren |
| 1997 | EuroPar | A Performance Tuning Approach for Shared-Memory Multiprocessors. | Per Stenstrm, Jonas Skeppstedt |
| 1996 | HPCA | Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. | Magnus Karlsson, Per Stenstrm |
| 1995 | HPCA | Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. | Fredrik Dahlgren, Per Stenstrm |
| 1995 | ISCA | Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. | Hkan Grahn, Per Stenstrm |
| 1994 | ASPLOS | Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols. | Jonas Skeppstedt, Per Stenstrm |
| 1994 | ICPP | Reducing the Write Traffic for a Hybrid Cache Protocol. | Fredrik Dahlgren, Per Stenstrm |
| 1994 | ICPP | An Integrated Methodology for the Verification of Directory-Based Cache Protocols. | Fong Pong, Per Stenstrm, Michel Dubois |
| 1994 | ISCA | Combined Performance Gains of Simple Cache Protocol Extensions. | Fredrik Dahlgren, Michel Dubois, Per Stenstrm |
| 1993 | ICPP | Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. | Fredrik Dahlgren, Michel Dubois, Per Stenstrm |
| 1993 | ISCA | The Detection and Elimination of Useless Misses in Multiprocessors. | Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenstrm |
| 1993 | ISCA | An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. | Per Stenstrm, Mats Brorsson, Lars Sandberg |
| 1992 | ISCA | Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. | Per Stenstrm, Truman Joe, Anoop Gupta |
| 1991 | ICPP | A Lockup-Free Multiprocessor Cache Design. | Per Stenstrm, Fredrik Dahlgren, Lars Lundberg |
| 1991 | MICRO | On Reconfigurable On-Chip Data Caches. | Fredrik Dahlgren, Per Stenstrm |
| 1989 | ISCA | A Cache Consistency Protocol for Multiprocessors with Multistage Networks. | Per Stenstrm |