Peter Celinski
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2002–2003
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2003 | ISCAS | Area efficient, high speed parallel counter circuits using charge recycling threshold logic. | Peter Celinski, Derek Abbott, Sorin Dan Cotofana |
| 2003 | IWANN | A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. | Peter Celinski, Sorin Cotofana, Derek Abbott |
| 2002 | ISCAS | Low depth carry lookahead addition using charge recycling threshold logic. | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Jos Francisco Lpez |