Peter Duzy
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1990–1992
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1992 | DAC | High-Level Synthesis from VHDL with Exact Timing Constraints. | A. Stoll, Peter Duzy |
| 1990 | ICCD | ASIC design using the high-level synthesis system CALLAS: a case study. | Michael Koster, Martin Geiger, Peter Duzy |