Ping-Heng Wu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2026–2026
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data Recovery in 40-nm CMOS. | Shuo Han, Sheng-You Liu, Kai-Hung Chou, Min-Shu Shih, Ping-Heng Wu, Ching-Yuan Yang |