Po-Hui Yang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
1998–2012
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISCAS | A fast wake-up power gating technique with inducing a balanced rush current. | Chao-Yang Chang, Pai-Cheng Tso, Chung-Hsun Huang, Po-Hui Yang |
| 2003 | ISCAS | A 2.5 V switched-current sigma-delta modulator with a novel class AB memory cell. | Shuenn-Yuh Lee, Yueh-Lun Tsai, Wei-Zen Su, Po-Hui Yang |
| 2000 | ASPDAC | Power analysis and implementation of a low-power 300 MHz 8-b 8-b pipelined multiplier. | Jinn-Shyan Wang, Po-Hui Yang |
| 2000 | ISCAS | A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. | Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang |
| 1998 | ISLPED | Low-power embedded SRAM macros with current-mode read/write operations. | Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng |