Prashant Dubey
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2007–2017
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ISCAS | A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision. | Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen |
| 2014 | VLSID | A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. | Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja |
| 2013 | VLSID | 38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS. | Prashant Dubey, Rashmi Agarwal |
| 2013 | VLSID | PODIA: Power Optimization through Differential Imbalanced Amplifier. | Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha |
| 2007 | DDECS | Built in Defect Prognosis for Embedded Memories. | Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani |
| 2007 | ISCAS | GALS Based Shared Test Architecture for Embedded Memories. | Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani |