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Prashant J. Nair

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

46

Venues

12

Active years

2013–2026

Best venue rank

A*

Where they publish

Papers

46 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCAEarly Silicon of Raptor: The First 3D-DRAM Accelerator for Generative Inference.Prashant J. Nair, Ramyad Hadidi, Subramani Ganesh, Sangamesh Kodge, Shubhankit Rathore, Neil Thanawala, Nikitha Reddy, Gyanesh Saharia, Vinayak Patankar, Arun Tiruvur, Nithesh Kurella, Sudeep Bhoja
2026ISCATranspiler-Architecture Co-Design to Curb Clifford Costs in Fault-Tolerant Quantum Computing.Meng Wang, Chenxu Liu, Samuel A. Stein, Yufei Ding, Poulami Das, Prashant J. Nair, Ang Li
2026ISCALoaded Dice: Solving the Non-Selection Problem for Scalable Probabilistic RowHammer Defense.Jeonghyun Woo, Junsu Kim, Aamer Jaleel, Prashant J. Nair
2026SACMATThe Memory Substrate of Tomorrow: Resilient DRAM for Secure and Intelligent Computing.Prashant J. Nair
2025DATESlipstream: Semantic-Based Training Acceleration for Recommendation Models.Yassaman Ebrahimzadeh Maboud, Muhammad Adnan, Divya Mahajan, Prashant J. Nair
2025HPCAQPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues.Jeonghyun Woo, Shaopeng Chris Lin, Prashant J. Nair, Aamer Jaleel, Gururaj Saileshwar
2025HPCADAPPER: A Performance-Attack-Resilient Tracker for RowHammer Defense.Jeonghyun Woo, Prashant J. Nair
2025ICMLDialogue Without Limits: Constant-Sized KV Caches for Extended Response in LLMs.Ravi Ghadia, Avinash Kumar, Gaurav Jain, Prashant J. Nair, Poulami Das
2025ISCAAccelerating Simulation of Quantum Circuits under Noise via Computational Reuse.Meng Wang, Swamit Tannu, Prashant J. Nair
2025ISCAAvalanche: Optimizing Cache Utilization via Matrix Reordering for Sparse Matrix Multiplication Accelerator.Gwangeun Byeon, Seongwook Kim, Hyungjin Kim, Sukhyun Han, Jinkwon Kim, Prashant J. Nair, Taewook Kang, Seokin Hong
2025ISCAMagellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access.Gelin Fu, Tian Xia, Mingzhuo Yin, Prashant J. Nair, Mieszko Lis, Pengju Ren
2025MICRORayN: Ray Tracing Acceleration with Near-memory Computing.Mohammadreza Saed, Prashant J. Nair, Tor M. Aamodt
2024ASPLOSRed-QAOA: Efficient Variational Optimization through Circuit Reduction.Meng Wang, Bo Fang, Ang Li, Prashant J. Nair
2024CLUSTERUnderstanding Mixed Precision GEMM with MPGemmFI: Insights into Fault Resilience.Bo Fang, Xinyi Li, Harvey Dam, Cheng Tan, Siva Kumar Sastry Hari, Timothy Tsai, Ignacio Laguna, Dingwen Tao, Ganesh Gopalakrishnan, Prashant J. Nair, Kevin J. Barker, Ang Li
2024ISCAHeterogeneous Acceleration Pipeline for Recommendation System Training.Muhammad Adnan, Yassaman Ebrahimzadeh Maboud, Divya Mahajan, Prashant J. Nair
2024MICROQoncord: A Multi-Device Job Scheduling Framework for Variational Quantum Algorithms.Meng Wang, Poulami Das, Prashant J. Nair
2024MICROA Case for Speculative Address Translation with Rapid Validation for GPUs.Junhyeok Park, Osang Kwon, Yongho Lee, Seongwook Kim, Gwangeun Byeon, Jihun Yoon, Prashant J. Nair, Seokin Hong
2024QCECircInspect: Integrating Visual Circuit Analysis, Abstraction, and Real-Time Development in Quantum Debugging.Mushahid Khan, Prashant J. Nair, Olivia Di Matteo
2023ASPLOSHuffDuff: Stealing Pruned DNNs from Sparse Accelerators.Dingqing Yang, Prashant J. Nair, Mieszko Lis
2023HPCAScalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems.Jeonghyun Woo, Gururaj Saileshwar, Prashant J. Nair
2023SCStructural Coding: A Low-Cost Scheme to Protect CNNs from Large-Granularity Memory Faults.Ali Asgari Khoshouyeh, Florian Geissler, Syed Sha Qutub, Michael Paulitsch, Prashant J. Nair, Karthik Pattabiraman
2023SCEnabling Scalable VQE Simulation on Leading HPC Systems.Meng Wang, Fei Hua, Chenxu Liu, Nicholas P. Bauman, Karol Kowalski, Daniel Claudino, Travis S. Humble, Prashant J. Nair, Ang Li
2022ASPLOSRandomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows.Gururaj Saileshwar, Bolin Wang, Moinuddin K. Qureshi, Prashant J. Nair
2022HPCASafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection.Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi
2022ISCAHydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking.Moinuddin K. Qureshi, Aditya Rohan, Gururaj Saileshwar, Prashant J. Nair
2022MICROAQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime.Anish Saxena, Gururaj Saileshwar, Prashant J. Nair, Moinuddin K. Qureshi
2021DATEA Case for Emerging Memories in DNN Accelerators.Avilash Mukherjee, Kumar Saurav, Prashant J. Nair, Sudip Shekhar, Mieszko Lis
2020ASPLOSThesaurus: Efficient Cache Compression via Dynamic Clustering.Amin Ghasemazar, Prashant J. Nair, Mieszko Lis
2020DATE2DCC: Cache Compression in Two Dimensions.Amin Ghasemazar, Mohammad Ewais, Prashant J. Nair, Mieszko Lis
2020ICCDADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches.Beomjun Kim, Prashant J. Nair, Seokin Hong
2019DSNSuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.Prashant J. Nair, Bahar Asgari, Moinuddin K. Qureshi
2019MICROA Case for Multi-Programming Quantum Computers.Poulami Das, Swamit S. Tannu, Prashant J. Nair, Moinuddin K. Qureshi
2019MICROTouch: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.Seokin Hong, Blent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair
2018HPCASYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi
2018MICROMorphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Jos A. Joao, Moinuddin K. Qureshi
2017ISCADICE: Compressing DRAM Caches for Bandwidth and Capacity.Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi
2017MICROTaming the instruction bandwidth of quantum computers via hardware-managed error correction.Swamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi
2016HPCALow-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu
2016ISCAXED: Exposing On-Die Error Detection Information for Strong Memory Reliability.Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi
2015ASPLOSDEUCE: Write-Efficient Encryption for Non-Volatile Memories.Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi
2015DSNReducing Refresh Power in Mobile Devices with Morphable ECC.Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi
2015DSNAVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.Moinuddin K. Qureshi, Dae-Hyun Kim, Samira Manabi Khan, Prashant J. Nair, Onur Mutlu
2015HPCAReducing read latency of phase change memory via early read and Turbo Read.Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi
2014MICROCitadel: Efficiently Protecting Stacked Memory from Large Granularity Failures.Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi
2013HPCAA case for Refresh Pausing in DRAM memory systems.Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
2013ISCAArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi