Praveen Vellanki
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2004–2004
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | DATE | A Power and Performance Model for Network-on-Chip Architectures. | Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha |