| 2022 | DATE | CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance. | Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda |
| 2019 | DAC | DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. | Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli |
| 2019 | DATE | FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories. | Lokesh Siddhu, Preeti Ranjan Panda |
| 2019 | VLSID | Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. | Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri |
| 2018 | VLSID | Exploration of Loop Unroll Factors in High Level Synthesis. | Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh |
| 2017 | DATE | A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. | Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney |
| 2017 | DATE | Reusing trace buffers to enhance cache performance. | Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi |
| 2016 | ASPDAC | Extending trace history through tapered summaries in post-silicon validation. | Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi |
| 2016 | DATE | Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. | Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney |
| 2016 | VLSID | A Generic Implementation of Barriers Using Optical Interconnects. | Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi |
| 2015 | VLSID | Power Optimization Techniques for DDR3 SDRAM. | Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma |
| 2014 | ASPDAC | Array scalarization in high level synthesis. | Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan |
| 2014 | DATE | Energy optimization in Android applications through wakelock placement. | Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan |
| 2014 | DATE | Energy efficient data flow transformation for Givens Rotation based QR Decomposition. | Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor |
| 2013 | CASES | SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems. | Prasenjit Chakraborty, Preeti Ranjan Panda |
| 2013 | DATE | Space sensitive cache dumping for post-silicon validation. | Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda |
| 2013 | ICASSP | Data memory optimization in LTE downlink. | Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor |
| 2013 | VLSID | Power Supply Efficiency Aware Server Allocation in Data Centers. | Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan |
| 2012 | CASES | Integrating software caches with scratch pad memory. | Prasenjit Chakraborty, Preeti Ranjan Panda |
| 2011 | FDL | A UML based framework for efficient validation of TLM 2 models. | Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda |
| 2010 | VLSID | Front-End Design Flows for Systems on Chip: An Embedded Tutorial. | Anshul Kumar, Preeti Ranjan Panda |
| 2009 | DAC | Online cache state dumping for processor debug. | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
| 2009 | DATE | A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. | Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda |
| 2009 | DATE | Cache aware compression for processor debug support. | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
| 2009 | ISVC | Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. | B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda |
| 2008 | ASPDAC | REWIRED - Register Write Inhibition by Resource Dedication. | Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda |
| 2008 | ICCAD | Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. | B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran |
| 2007 | DATE | The impact of loop unrolling on controller delay in high level synthesis. | Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda |
| 2007 | ISCAS | An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. | Rahul Jain, Preeti Ranjan Panda |
| 2007 | VLSID | Power Reduction in VLIW Processor with Compiler Driven Bypass Network. | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
| 2007 | VLSID | Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. | Rahul Jain, Preeti Ranjan Panda |
| 2007 | VLSID | Customization of Register File Banking Architecture for Low Power. | Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda |
| 2006 | ASPDAC | Abridged addressing: a low power memory addressing strategy. | Preeti Ranjan Panda |
| 2006 | DAC | Rapid estimation of control delay from high-level specifications. | Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda |
| 2005 | DATE | Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
| 2005 | VLSID | Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. | Vikram Singh Saun, Preeti Ranjan Panda |
| 2003 | VLSID | Specification and Design of Multi-Million Gate SOCs. | Ramesh Chandra, Preeti Ranjan Panda, Jrg Henkel, Sri Parameswaran, Loganath Ramachandran |
| 2002 | DAC | An integrated algorithm for memory allocation and assignment in high-level synthesis. | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
| 2002 | HiPC | Memory Architectures for Embedded Systems-On-Chip. | Preeti Ranjan Panda, Nikil D. Dutt |
| 2002 | ICCAD | An energy-conscious algorithm for memory port allocation. | Preeti Ranjan Panda, Lakshmikantam Chitturi |
| 2001 | VLSID | Embedded Memories in System Design: Technology, Application, Design and Tools. | Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda |
| 1999 | ICCAD | Memory bank customization and assignment in behavioral synthesis. | Preeti Ranjan Panda |
| 1998 | DATE | Data Cache Sizing for Embedded Processor Applications. | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
| 1997 | DATE | Efficient utilization of scratch-pad memory in embedded processor applications. | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
| 1997 | ICCAD | Exploiting off-chip memory access modes in high-level synthesis. | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
| 1997 | ICCD | A Data Alignment Technique for Improving Cache Performance. | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau |
| 1997 | VLSID | Behavioral Array Mapping into Multiport Memories Targeting Low Power. | Preeti Ranjan Panda, Nikil D. Dutt |
| 1996 | DATE | Reducing Address Bus Transitions for Low Power Memory Mapping. | Preeti Ranjan Panda, Nikil D. Dutt |
| 1996 | ISLPED | Low-power mapping of behavioral arrays to multiple memories. | Preeti Ranjan Panda, Nikil D. Dutt |
| 1992 | VLSID | Estimating the Complexity of Synthesized Designs from FSM Specifications. | Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri |
| 1991 | ICCAD | A Flexible Scheme for State Assignment Based on Characteristics of the FSM. | Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri |