Purushotham Murugappa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
4
Active years
2011–2019
Best venue rank
C
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | DSD | A Reconfigurable Architecture for Posit Arithmetic. | Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony |
| 2013 | DATE | Parameterized area-efficient multi-standard turbo decoder. | Purushotham Murugappa, Amer Baghdadi, Michel Jzquel |
| 2013 | DSD | Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. | Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hbner, Jean-Philippe Diguet |
| 2013 | ISCAS | Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. | Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hbner |
| 2013 | RSP | Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. | Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jzquel |
| 2012 | RSP | FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. | Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jzquel |
| 2011 | DATE | A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. | Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jzquel |
| 2011 | RSP | Area and throughput optimized ASIP for multi-standard turbo decoding. | Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jzquel |