| 2026 | DATE | LiveVerilogEval: Contamination Free and Automatically Scalable Benchmark for Verilog Code Generation. | Charles Young, Hao Yu, Dezhi Ran, Qingchen Zhai, Tianqi Qiu, Frank Qu, Bangyan Wang, Yuan Xie, Tao Xie |
| 2026 | DATE | Towards Trustworthy LLM-Based Assertion Generation: A Data Augmentation Framework with Formal Check Approach. | Qingchen Zhai, Hao Yu, Chen Bai, Charles Young, Frank Qu, Dezhi Ran, Yuan Xie, Tao Xie |
| 2026 | ISCAS | Boosting Vector Instruction Throughput in RISC-V via a Hybrid Decoupled Architecture with VLIW-Driven Execution. | Weiying Wang, Qingchen Zhai, Ruozhou Xiao, Zhiwei Zhang |
| 2026 | ISCAS | RTCore: A RISC-V Processor Featuring Nested Hardware Loop Optimization for Real-time Control System. | Qingchen Zhai, Weiying Wang, Yueyue Wang, Yuanyang Xiang, Chen Xu, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang |
| 2026 | ISCAS | Breaking the Local Optima Barrier in Branch Predictor Design Space Exploration: An LLM-Based Initialization Strategy for PSO. | Qingchen Zhai, Chen Xu, Yuanyang Xiang, Yueyue Wang, Weiying Wang, Kunyu Zong, Jingshuai Jiang, Ruozhou Xiao, Zhiwei Zhang |
| 2025 | ISCAS | A Lightweight RISC-V Multi-Core Interaction Framework For Embedded Real-Time Applications. | Yuanyang Xiang, Chen Xu, Yueyue Wang, Weiying Wang, Qingchen Zhai, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang |
| 2025 | ISCAS | Using Greedy-Enhanced Heuristic to Optimize Instruction Scheduling for RISC-V DS. | Chen Xu, Yuanyang Xiang, Qingchen Zhai, Ruozhou Xiao, Zhiwei Zhang |
| 2025 | ISCAS | Instruction Level Parallelism Optimizations in a High-Performance Dual-Issue RISC-V Processor for Real-Time Control Systems. | Qingchen Zhai, Weiying Wang, Yueyue Wang, Yuanyang Xiang, Chen Xu, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang |