| 2017 | GI | A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. | Paul R. Genler, Oliver Knodel, Rainer G. Spallek |
| 2017 | GI | First Workshop on Hardware Defined Programming - HDP. | Oliver Knodel, Steffen Khler, Marko Rler, Rainer G. Spallek |
| 2017 | GI | Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. | Steffen Khler, Rainer G. Spallek |
| 2015 | DSD | Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. | Oliver Knodel, Rainer G. Spallek |
| 2015 | GI | Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wrterbuchansatz. | Kai-Uwe Irrgang, Thomas B. Preuer, Rainer G. Spallek |
| 2014 | FPL | Educating hardware design - From primary school children to postgraduate engineers. | Oliver Knodel, Martin Zabel, Patrick Lehmann, Rainer G. Spallek |
| 2014 | FPL | Ready PCIe data streaming solutions for FPGAs. | Thomas B. Preuer, Rainer G. Spallek |
| 2013 | FPL | Integration of a multi-FPGA system in a common cluster environment. | Oliver Knodel, Rainer G. Spallek |
| 2013 | FPL | Weasel: A platform-independent streaming-optimized SATA controller. | Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Khler, Thomas B. Preuer, Rainer G. Spallek |
| 2013 | ICPP | Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures. | Oliver Knodel, Andy Georgi, Patrick Lehmann, Wolfgang E. Nagel, Rainer G. Spallek |
| 2013 | VEE | Superblock compilation and other optimization techniques for a Java-based DPT machine emulator. | Marco Kaufmann, Rainer G. Spallek |
| 2012 | FCCM | Short-Read Mapping by a Systolic Custom FPGA Computation. | Thomas B. Preuer, Oliver Knodel, Rainer G. Spallek |
| 2011 | ARITH | Accelerating Computations on FPGA Carry Chains by Operand Compaction. | Thomas B. Preuer, Martin Zabel, Rainer G. Spallek |
| 2010 | FPL | Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. | Thomas B. Preuer, Rainer G. Spallek |
| 2009 | DATE | Generating the trace qualification configuration for MCDS from a high level language. | Jens Braunes, Rainer G. Spallek |
| 2009 | FPL | Mapping basic prefix computations to fast carry-chain structures. | Thomas B. Preuer, Rainer G. Spallek |
| 2007 | DSD | Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. | Martin Zabel, Thomas B. Preuer, Peter Reichel, Rainer G. Spallek |
| 2004 | FPL | Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. | Steffen Khler, Jens Braunes, Thomas Preuer, Martin Zabel, Rainer G. Spallek |
| 2003 | FPL | Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. | Sergej Sawitzki, Rainer G. Spallek |
| 2002 | FPL | A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. | Sebastian Friebe, Steffen Khler, Rainer G. Spallek, Henrik Juhr, Klaus Knanz |
| 2001 | FPL | Prototyping Framework for Reconfigurable Processors. | Sergej Sawitzki, Steffen Khler, Rainer G. Spallek |
| 2000 | FPL | Formal Verification of a Reconfigurable Microprocessor. | Sergej Sawitzki, Jens Schnherr, Rainer G. Spallek, Bernd Straube |
| 1999 | FPL | A Concept for an Evaluation Framework for Reconfigurable Systems. | Sergej Sawitzki, Rainer G. Spallek |
| 1998 | FPL | Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. | Sergej Sawitzki, Achim Gratz, Rainer G. Spallek |