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Rajeev Balasubramonian

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

60

Venues

13

Active years

2000–2025

Best venue rank

A*

Where they publish

Papers

60 indexed papers, newest first.

YearVenueTitleAuthors
2025ASPLOSFLEXPROF: Flexible, Side-Channel-Free Memory Access.Jarrett Minton, Rajeev Balasubramonian
2024ASPLOSPATHFINDER: Practical Real-Time Learning for Data Prefetching.Lin Jia, James Patrick Mcmahon, Sumanth Gudaparthi, Shreyas Singh, Rajeev Balasubramonian
2024SPHyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference.Sarabjeet Singh, Shreyas Singh, Sumanth Gudaparthi, Xiong Fan, Rajeev Balasubramonian
2022HPCACANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe
2022ICDEEfficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract).Zhao Chang, Dong Xie, Feifei Li, Jeff M. Phillips, Rajeev Balasubramonian
2021FCCMONT-X: An FPGA Approach to Real-time Portable Genomic Analysis.C. N. Ramachandra, Anirban Nag, Rajeev Balasubramonian, Gurpreet S. Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney
2021ISCADv: Improving DRAM Reliability and Performance On-Demand via Coherent Replication.Adarsh Patil, Vijay Nagarajan, Rajeev Balasubramonian, Nicolai Oswald
2021MICROOrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations.Anirban Nag, Rajeev Balasubramonian
2020ISCASpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks.Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2020ISCACompact Leakage-Free Support for Integrity and Reliability.Meysam Taassori, Rajeev Balasubramonian, Siddhartha Chhabra, Alaa R. Alameldeen, Manjula Peddireddy, Rajat Agarwal, Ryan Stutsman
2019ASPLOSρ: Relaxed Hierarchical ORAM.Chandrasekhar Nagarajan, Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari
2019ISPASSThe POP Detector: A Lightweight Online Program Phase Detection Framework.Karl Taht, James Greensky, Rajeev Balasubramonian
2019MICROWire-Aware Architecture and Dataflow for CNN Accelerators.Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2019MICROGenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment.Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2018ASPLOSVAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian
2018HPCASecure DIMM: Moving ORAM Primitives Closer to Memory.Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, Feifei Li
2018ISCAAn MLP-aware leakage-free memory controller.Andrew Vuong, Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian
2017IJCNNINXS: Bridging the throughput and energy gap for spiking neural networks.Surya Narayanan, Ali Shafiee, Rajeev Balasubramonian
2016ICCDEnabling technologies for memory compression: Metadata, mapping, and prediction.Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber
2016ICCDUnderstanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian
2016ISCAISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar
2016ISPASSAddressing service interruptions in memory with thread-to-rank assignment.Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim
2015HPCAOvercoming the challenges of crossbar resistive memory architectures.Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2015ICCDFixed-function hardware sorting accelerators for near data MapReduce execution.Seth H. Pugsley, Arjun Deb, Rajeev Balasubramonian, Feifei Li
2015ICCDImproving memristor memory with sneak current sharing.Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon
2015MICROAvoiding information leakage in the memory controller with fixed service policies.Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian, Mohit Tiwari
2015MICROEfficiently prefetching complex address patterns.Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti
2014HPCASandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian
2014HPCAMemZip: Exploring unconventional benefits from memory compression.Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis
2014ISCAMemory bandwidth reservation in the cloud to avoid information leakage in the memory controller.Akhila Gundu, Gita Sreekumar, Ali Shafiee, Seth H. Pugsley, Hardik B. Jain, Rajeev Balasubramonian, Mohit Tiwari
2014ISPASSNDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li
2014SCManaging DRAM Latency Divergence in Irregular GPGPU Applications.Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
2013HPCAA novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian
2013MICROQuantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi
2012HPCAEfficient scrub mechanisms for error-prone emerging memories.Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan
2012HPCAStaged Reads: Mitigating the impact of DRAM writes on DRAM reads.Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2012ISCALOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2012MICROLeveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi R. Iyer
2011ISCACombining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2010ASPLOSMicro-pages: increasing DRAM efficiency with locality-aware data placement.Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis
2010HPCACHOP: Adaptive filter-based DRAM caching for CMP server platforms.Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian
2010HPCATowards scalable, energy-efficient, bus-based on-chip networks.Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2010ISCAImproving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.David W. Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian
2010ISCARethinking DRAM design and organization for energy-constrained multi-cores.Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2010ISPASSHardware prediction of OS run-length for fine-grained resource customization.David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand
2009HiPCNon-uniform power access in large caches with low-swing wires.Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2009HPCADynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter
2009HPCAOptimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell
2007ISCAInterconnect design considerations for large NUCA caches.Naveen Muralimanohar, Rajeev Balasubramonian
2007MICROLeveraging 3D Technology for Improved Reliability.Niti Madan, Rajeev Balasubramonian
2007MICROOptimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2006ISCAInterconnect-Aware Coherence Protocols for Chip Multiprocessors.Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
2006ISPASSPower efficient resource scaling in partitioned architectures through dynamic heterogeneity.Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian
2005HPCAMicroarchitectural Wire Management for Performance and Power in Partitioned Architectures.Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
2004ICSCluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.Rajeev Balasubramonian
2003ISCADynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2002HPCAEnergy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
2001ISCADynamically allocating processor resources between nearby and distant ILP.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2001MICROReducing the complexity of the register file in dynamic superscalar processors.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2000MICROMemory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas