Rajesh Amratlal Thakker
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2009–2019
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | VLSID | Parasitic-Aware Automatic Analog CMOS Circuit Design Environment. | Subhash Jagadishchandra Patel, Rajesh Amratlal Thakker |
| 2018 | VLSID | Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm. | Subhash J. Patel, Rajesh Amratlal Thakker |
| 2017 | VLSID | Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology. | Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari |
| 2009 | ASPDAC | Automated design and optimization of circuits in emerging technologies. | Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil |
| 2009 | VLSID | Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization. | Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil |