Rajshekar Kalayappan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
2017–2024
Best venue rank
B
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ASPDAC | On Decomposing Complex Test Cases for Efficient Post-silicon Validation. | C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan |
| 2024 | HiPC | CaH2: Criticality aware Hybrid L2. | Shruthi Karunakar, Rajshekar Kalayappan |
| 2024 | RV | faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties. | Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade, Piyush P. Kurur |
| 2023 | VLSID | SANNA: Secure Acceleration of Neural Network Applications. | Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran |
| 2017 | DATE | A hardware implementation of the MCAS synchronization primitive. | Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi |