| 2019 | ETFA | Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer. | Rubn Nieto, Ral Mateos, lvaro Hernndez, Edel Daz |
| 2019 | IECON | Virtual Platform of FPGA based MPSoC for Power Electronics Applications: OS simulation. | Edel Daz, Ral Mateos, Emilio Jos Bueno |
| 2015 | ETFA | Study of suitable filter architectures for FBMC techniques applied to PLC communications. | Pablo Poudereux, Ral Mateos, lvaro Hernndez, Francisco Nombela, Fernando Cruz-Roldn |
| 2014 | ETFA | FPGA-based implementation of a filter bank-based transmultiplexer for multicarrier communications. | Pablo Poudereux, Ral Mateos, lvaro Hernndez, Fernando Cruz-Roldn, David Oses |
| 2013 | IECON | Comparative of HLS and HDL implementations of a grid synchronization algorithm. | Fco. Manuel Snchez, Ral Mateos, Emilio Jos Bueno, Javier Mingo, Ines Sanz |
| 2003 | ETFA | Different proposals to the multiplication of 33 vision mask in VHDL for FPGA's. | Ignacio Bravo Muoz, lvaro Hernndez, Alfredo Gardel Vicente, Ral Mateos, Jos Luis Lzaro, V. Diaz |
| 2003 | ETFA | Lossless implementation in VHDL of an image wavelet transform. | Ral Mateos, Alfredo Gardel Vicente, lvaro Hernndez, Ignacio Bravo Muoz, C. Garcia |