| 2008 | VLSID | An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. | Terrell R. Bennett, Rama Sangireddy |
| 2008 | VLSID | Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. | Hui Wang, Sandeep Baldawa, Rama Sangireddy |
| 2007 | ISCAS | Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. | Jatan P. Shah, Rama Sangireddy |
| 2006 | IPCCC | High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. | Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy |
| 2006 | ISCAS | Fast and low-power processor front-end with reduced rename logic circuit complexity. | Rama Sangireddy |
| 2006 | VLSID | Performance Optimization with Scalable Reconfigurable Computing Systems. | Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam |
| 2004 | ICCD | Exploiting Quiescent States in Register Lifetime. | Rama Sangireddy, Arun K. Somani |
| 2003 | HiPC | Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures. | Rama Sangireddy, Huesung Kim, Arun K. Somani |
| 2003 | ICCCN | Scalable, memory efficient, high-speed lookup and update algorithms for IP routing. | Natsuhiko Futamura, Rama Sangireddy, Srinivas Aluru, Arun K. Somani |
| 2002 | HiPC | Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. | Rama Sangireddy, Huesung Kim, Arun K. Somani |
| 2001 | ICCCN | Binary decision diagrams for efficient hardware implementation of fast IP routing lookups. | Rama Sangireddy, Arun K. Somani |