| 2020 | ICCD | WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. | Leonid Yavits, Lois Orosa, Suyash Mahar, Joo Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu |
| 2020 | SYSTOR | BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. | Roman Kaplan, Leonid Yavits, Ran Ginosar |
| 2019 | CCS | SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. | Leonid Azriel, Ran Ginosar, Avi Mendelson |
| 2016 | ISCA | Using Scan Side Channel for Detecting IP Theft. | Leonid Azriel, Ran Ginosar, Shay Gueron, Avi Mendelson |
| 2014 | ISCA | Hardware Scheduler Performance on the Plural Many-Core Architecture. | Itai Avron, Ran Ginosar |
| 2013 | DATE | Metastability challenges for 65nm and beyond: simulation and measurements. | Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar |
| 2012 | HPCC | Performance of a Hardware Scheduler for Many-core Architecture. | Itai Avron, Ran Ginosar |
| 2012 | ISCAS | Energy metrics for power efficient crosslink and mesh topologies. | Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny |
| 2011 | ISCAS | An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. | Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny |
| 2009 | INFOCOM | The Capacity Allocation Paradox. | Asaf Baron, Ran Ginosar, Isaac Keslassy |
| 2009 | MICRO | Multiple clock and voltage domains for chip multi processors. | Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser |
| 2007 | DATE | Routing table minimization for irregular mesh NoCs. | Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
| 2006 | DATE | Efficient link capacity and QoS design for network-on-chip. | Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
| 2005 | ISCAS | Low-leakage repeaters for NoC interconnects. | Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
| 2005 | ISCAS | Low energy asynchronous architectures. | Ilya Obridko, Ran Ginosar |
| 2004 | DATE | Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. | Alex Branover, Rakefet Kol, Ran Ginosar |
| 2002 | PIMRC | Parallel VLSI architecture for MAP turbo decoder. | Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar |
| 1999 | DAC | CAD Directions for High Performance Asynchronous Circuits. | Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken |
| 1998 | ICCD | Adaptive synchronization. | Ran Ginosar, Rakefet Kol |
| 1998 | ICS | Untitled record | Rakefet Kol, Ran Ginosar |
| 1998 | ISLPED | A low power video processor. | Uzi Zangi, Ran Ginosar |
| 1997 | ICCD | A Double-Latched Asynchronous Pipeline. | Rakefet Kol, Ran Ginosar |
| 1994 | ICPR | Adaptive sensitivity CCD image sensor. | Sarit Chen, Ran Ginosar |
| 1994 | ICPR | Spatio-chromatic model for colour image processing. | Stuart G. Wolf, Ran Ginosar, Yehoshua Y. Zeevi |
| 1991 | ICLP | CARMEL-4: The Unify-Spawn Machine for FCP. | Arie Harsat, Ran Ginosar |
| 1990 | ICLP | An Extended RISC Methodology and its Application to FCP. | Arie Harsat, Ran Ginosar |
| 1990 | VCIP | Foveating vision systems architecture: image acquisition and display. | Yehoshua Y. Zeevi, Ran Ginosar |
| 1985 | ICPP | Design and Implementation of Switching Systems for Parallel Processors. | Ran Ginosar, Dwight D. Hill |
| 1981 | ISCA | MP/C: A Multiprocessor/Computer Architecture. | Bruce W. Arden, Ran Ginosar |
| 1981 | ISCA | A Single-Relation Module for a Data Base Machine. | Bruce W. Arden, Ran Ginosar |