Ratnala Vinay
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2025–2025
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | Digital Twin Assisted Performance Aware Power Management for FPGA MPSoC using High Speed Reinforcement Learning. | Kartik Laad, Ratnala Vinay, Parveen Nisha, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya |
| 2025 | ISCAS | Digital Twin-Based Architecture for Run-Time Power Modeling for Sensorless Edge Devices. | Parveen Nisha, Ratnala Vinay, Kartik Laad, Amit Acharyya |