Digital Twin Assisted Performance Aware Power Management for FPGA MPSoC using High Speed Reinforcement Learning.
Kartik Laad, Ratnala Vinay, Parveen Nisha, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya
Browse the full ISCAS paper archive.
Kartik Laad, Ratnala Vinay, Parveen Nisha, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya
Browse the full ISCAS paper archive.