| 2024 | ISPASS | Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. | Abhishek Tyagi, Reiley Jeyapaul, Chuteng Zhou, Paul N. Whatmough, Yuhao Zhu |
| 2018 | DATE | LASER: A hardware/software approach to accelerate complicated loops on CGRAs. | Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul |
| 2015 | DAC | Guidelines to design parity protected write-back L1 data cache. | Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava |
| 2014 | DAC | Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. | Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu |
| 2011 | CASES | Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. | Reiley Jeyapaul, Aviral Shrivastava |
| 2011 | ICPP | UnSync: A Soft Error Resilient Redundant Multicore Architecture. | Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee |
| 2011 | ICPP | Enabling Multithreading on CGRAs. | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula |
| 2010 | SCOPES | B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. | Reiley Jeyapaul, Aviral Shrivastava |
| 2009 | VLSID | Code Transformations for TLB Power Reduction. | Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava |
| 2008 | ASPDAC | SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek |