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Ren-Shuo Liu

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

24

Venues

11

Active years

2012–2026

Best venue rank

A*

Where they publish

Papers

24 indexed papers, newest first.

YearVenueTitleAuthors
2026ASPDACInput Reuse, Weight-Stationary Dataflow and Mapping Strategy for Depthwise Convolution in Computing-in-Memory Neural Network Accelerators.Chia-Chun Wang, Yu-Chih Tsai, Ren-Shuo Liu
2026ISCASClipping Error Compensation for Accuracy Recovery and Throughput Improvement in Computing-in-Memory.Yu-Chih Tsai, Hsuan-Hung Shen, Ren-Shuo Liu
2026ISCASAdaptive Row-wise Attention Score Pruning and Compensation for Attention Acceleration.Chia-Chun Wang, Yu-Lin Lin, Ren-Shuo Liu
2026ISCASReliability and Optimization for Neural Network Accelerators using Value-Aware Error-Marking Pattern with Sequential Access Error Correction.Jun-Shen Wu, Ren-Shuo Liu
2025ICCDDMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment.Yu-Chih Tsai, Chia-Cheng Chang, Ren-Shuo Liu
2025ICCDAccess Frequency-Aware Storage Reduction for Deep Learning Recommendation Model.Chia-Chun Wang, Chuan-Yao Lai, Ren-Shuo Liu
2023DACBit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference.Yun-Chen Lo, Ren-Shuo Liu
2023DACMorphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture.Yun-Chen Lo, Ren-Shuo Liu
2023DATEBuilt-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory.Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu
2023ICCDBICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed!Yun-Chen Lo, Chia-Chun Wang, Ren-Shuo Liu
2023ICCDCNN Inference Accelerators with Adjustable Feature Map Compression Ratios.Yu-Chih Tsai, Chung-Yueh Liu, Chia-Chun Wang, Tsen-Wei Hsu, Ren-Shuo Liu
2023ICCDExploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.Chia-Chun Wang, Yun-Chen Lo, Jun-Shen Wu, Yu-Chih Tsai, Chia-Cheng Chang, Tsen-Wei Hsu, Min-Wei Chu, Chuan-Yao Lai, Ren-Shuo Liu
2023ICCDFM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators.Jun-Shen Wu, Ren-Shuo Liu
2023ICLRBlock and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference.Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu
2023MICROBucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs.Yun-Chen Lo, Ren-Shuo Liu
2022ICCADISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu
2021ASPDACValue-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators.Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
2019USENIXOPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface.Yun-Sheng Chang, Ren-Shuo Liu
2018ASPDACDI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives.Jian-Hao Huang, Ren-Shuo Liu
2017ICCADVST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers.Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung
2014ASPLOSNVM duet: unified working memory and persistent store architecture.Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang
2014DACEC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
2013DACDuraCache: a durable SSD cache using MLC NAND flash.Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen
2012FASTOptimizing NAND flash-based SSDs via retention relaxation.Ren-Shuo Liu, Chia-Lin Yang, Wei Wu