| 2021 | DSD | Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. | Jakub Lojda, Richard Panek, Zdenek Kotsek |
| 2021 | DSD | Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. | Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotsek |
| 2020 | DDECS | Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. | Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotsek |
| 2020 | DSD | Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. | Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotsek |
| 2019 | DSD | Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. | Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotsek |
| 2018 | DSD | FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. | Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotsek |
| 2017 | DSD | Reliability Analysis and Improvement of FPGA-Based Robot Controller. | Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotsek |