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Ritchie Zhao

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

15

Venues

9

Active years

2015–2025

Best venue rank

A*

Where they publish

Papers

15 indexed papers, newest first.

YearVenueTitleAuthors
2025ICMLRocketKV: Accelerating Long-Context LLM Inference via Two-Stage KV Cache Compression.Payman Behnam, Yaosheng Fu, Ritchie Zhao, Po-An Tsai, Zhiding Yu, Alexey Tumanov
2025KDDResMoE: Space-efficient Compression of Mixture of Experts LLMs via Residual Restoration.Mengting Ai, Tianxin Wei, Yifan Chen, Zhichen Zeng, Ritchie Zhao, Girish Varatkar, Bita Darvish Rouhani, Xianfeng Tang, Hanghang Tong, Jingrui He
2023ISCAWith Shared Microexponents, A Little Shifting Goes a Long Way.Bita Darvish Rouhani, Ritchie Zhao, Venmugil Elango, Rasoul Shafipour, Mathew Hall, Maral Mesmakhosroshahi, Ankit More, Levi Melnick, Maximilian Golub, Girish Varatkar, Lai Shao, Gaurav Kolhe, Dimitry Melts, Jasmine Klar, Renee L'Heureux, Matt Perry, Doug Burger, Eric S. Chung, Zhaoxia (Summer) Deng, Sam Naghshineh, Jongsoo Park, Maxim Naumov
2020ICLRPrecision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations.Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
2019CVPRBuilding Efficient Deep Neural Networks With Unitary Group Convolutions.Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2019ICMLImproving Neural Network Quantization without Retraining using Outlier Channel Splitting.Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2018FPGARosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang
2017ACSSCEnabling adaptive loop pipelining in high-level synthesis.Steve Dai, Gai Liu, Ritchie Zhao, Zhiru Zhang
2017CVPRBinarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration.Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta
2017FPGADynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis.Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang
2017FPGAA Parallel Bandit-Based Approach for Autotuning FPGA Compilation.Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang
2017FPGAAccelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs.Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang
2016DACImproving high-level synthesis with decoupled data structure optimization.Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang
2015DACArea-efficient pipelining for FPGA-targeted high-level synthesis.Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang
2015ICCADElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests.Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang