Ronny Ronen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
12
Active years
1998–2024
Best venue rank
A*
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | MICRO | PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. | Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky |
| 2023 | HPCA | On Consistency for Bulk-Bitwise Processing-in-Memory. | Ben Perach, Ronny Ronen, Shahar Kvatinsky |
| 2022 | ISCAS | MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. | Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky |
| 2021 | DAC | Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. | Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky |
| 2020 | ICCAD | CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. | Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky |
| 2018 | DATE | Practical challenges in delivering the promises of real processing-in-memory machines. | Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky |
| 2014 | ISCA | Improving the energy efficiency of Big Cores. | Kenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc, Pradeep Dubey |
| 2009 | HiPC | Terascale chip multiprocessor memory hierarchy and programming model. | Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha |
| 2009 | PLDI | Programming model for a heterogeneous x86 platform. | Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson |
| 2004 | ICCD | Best of Both Latency and Throughput. | Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang |
| 2003 | ICS | Selecting long atomic traces for high coverage. | Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen |
| 2001 | ISLPED | Micro-operation cache: a power aware frontend for the variable instruction length ISA. | Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen |
| 2000 | HPCA | eXtended Block Cache. | Stphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen |
| 2000 | ISCA | Early load address resolution via register tracking. | Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stphan Jourdan, Maxim Kalaev, Ronny Ronen |
| 1999 | ISCA | Correlated Load-Address Predictors. | Michael Bekerman, Stphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser |
| 1999 | ISCA | Speculation Techniques for Improving Load Related Instruction Scheduling. | Adi Yoaz, Mattan Erez, Ronny Ronen, Stphan Jourdan |
| 1998 | MICRO | A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. | Stphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz |