Ruiyuan Guo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2026–2026
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping. | Ruiyuan Guo, Zexu Zhang, Chang Liu, Da Tang, Weiqi Shen, Haodong Lu, Xiqiong Bai, Kun Wang, Jianli Chen, Jun Yu |