RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping.
Ruiyuan Guo, Zexu Zhang, Chang Liu, Da Tang, Weiqi Shen, Haodong Lu, Xiqiong Bai, Kun Wang, Jianli Chen, Jun Yu
Browse the full DATE paper archive.
Ruiyuan Guo, Zexu Zhang, Chang Liu, Da Tang, Weiqi Shen, Haodong Lu, Xiqiong Bai, Kun Wang, Jianli Chen, Jun Yu
Browse the full DATE paper archive.