| 2025 | ISCAS | A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node. | Kai-Jie Tong, Ting-An Jian, Shang-Mou Zhou, Yi-Jia Wu, Bo-Xiang Yang, Meng-Ru Lin, Ming-Yi Huang, Shi-Xian Tang, Ya-Zhu Yang, Zheng-Jie Peng, Yu-Cheng Lin, Rung-Bin Lin |
| 2024 | ISCAS | Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses. | Rung-Bin Lin, Pei-Sheng Lu |
| 2017 | ICCAD | Overview of the 2017 CAD contest at ICCAD: Invited paper. | Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake |
| 2016 | DATE | Practical ILP-based routing of standard cells. | Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin |
| 2016 | ICCAD | Overview of the 2016 CAD contest at ICCAD. | Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake |
| 2015 | DATE | Simultaneous transistor pairing and placement for CMOS standard cells. | Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin |
| 2015 | ICCAD | Overview of the 2015 CAD Contest at ICCAD. | Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim |
| 2013 | DATE | Slack budgeting and slack to length converting for multi-bit flip-flop merging. | Chia-Chieh Lu, Rung-Bin Lin |
| 2012 | DATE | Design and analysis of via-configurable routing fabrics for structured ASICs. | Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai |
| 2011 | DATE | Clock gating optimization with delay-matching. | Shih-Jung Hsu, Rung-Bin Lin |
| 2010 | DATE | Power gating design for standard-cell-like structured ASICs. | Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin |
| 2008 | ICCD | Router and cell library co-development for improving redundant via insertion at pins. | Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin |
| 2007 | DATE | Double-via-driven standard cell library design. | Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin |
| 2007 | DDECS | Reticle Exposure Plans for Multi-Project Wafers. | Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu |
| 2006 | ASPDAC | Design space exploration for minimizing multi-project wafer production cost. | Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai |
| 2006 | ISCAS | Is more redundancy better for on-chip bus encoding. | Hsun-Chieh Yu, Rung-Bin Lin |
| 2005 | ISCAS | A divide-and-conquer approach to estimating minimum/maximum leakage current. | Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin |
| 2005 | ISCAS | Coupling reduction analysis of bus-invert coding. | Rung-Bin Lin |
| 2005 | ISCAS | Multiple project wafers for medium-volume IC production. | Meng-Chiou Wu, Rung-Bin Lin |
| 2004 | ISCAS | Multi-layer constrained via minimization with conjugate conflict continuation graphs. | Rung-Bin Lin, Shuyu Chen |
| 2003 | VLSID | A Low Power-Delay Product Page-Based Address Bus Coding Method. | Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin |
| 2002 | VLSID | Weight-Based Bus-Invert Coding for Low-Power Applications. | Rung-Bin Lin, Chi-Ming Tsai |
| 2002 | VLSID | An Adaptive Interconnect-Length Driven Placer. | Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin |
| 1999 | ASPDAC | Low Power CMOS Off-Chip Drivers with Slew-rate Difference. | Rung-Bin Lin, Jinq-Chang Chen |
| 1999 | ASPDAC | Benchmark Circuits Improve the Quality of a Standard Cell Library. | Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai |
| 1998 | VLSID | A New Statistical Approach to Timing Analysis of VLSI Circuits. | Rung-Bin Lin, Meng-Chiou Wu |
| 1992 | DAC | Fuzzy Logic Approach to Placement Problem. | Rung-Bin Lin, Eugene Shragowitz |