S. Ramanathan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
2
Active years
1990–1999
Best venue rank
National
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | VLSID | Synthesis of Configurable Architectures for DSP Algorithms. | S. Ramanathan, V. Visvanathan, S. K. Nandy |
| 1997 | VLSID | Low-Power Configurable Processor Array for DLMS Adaptive Filtering. | S. Ramanathan, V. Visvanathan |
| 1996 | VLSID | A systolic architecture for LMS adaptive filtering with minimal adaptation delay. | S. Ramanathan, V. Visvanathan |
| 1995 | VLSID | A modular systolic architecture for delayed least mean squares adaptive filtering. | V. Visvanathan, S. Ramanathan |
| 1993 | VLSID | A Methodology for Generating Application Specific Tree Multipliers. | S. Ramanathan, Nibedita Mohanty, V. Visvanathan |
| 1993 | VLSID | An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. | V. Visvanathan, Nibedita Mohanty, S. Ramanathan |
| 1990 | FORTE | Rewrite Systems for Protocol Specification and Verification. | S. Ramanathan, G. Sivakumar |