| 2024 | ASPDAC | MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. | Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant |
| 2024 | VLSID | Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. | Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana |
| 2023 | ASPDAC | Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. | Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant |
| 2023 | ISLPED | IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. | Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik |
| 2020 | VLSID | FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. | Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar |
| 2019 | PACT | Computational Issues in Construction of 4-D Projective Spaces with Perfect Access Patterns for Higher Primes. | Shreeniwas N. Sapre, Sachin B. Patkar, Supratim Biswas |
| 2018 | VLSID | Lightweight Forth Programmable NoCs. | Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar |
| 2016 | VLSID | Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. | Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar |
| 2015 | VLSID | Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video. | Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar |
| 2014 | ICCD | Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. | Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar |
| 2013 | VLSID | Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. | Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar |
| 2012 | VLSID | Two Graph Based Circuit Simulator for PDE-Electrical Analogy. | Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar |
| 2009 | HiPC | Acceleration of conjugate gradient method for circuit simulation using CUDA. | Anirudh Maringanti, Viraj Athavale, Sachin B. Patkar |
| 2009 | ISCAS | A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms. | Dinesh Baviskar, Sachin B. Patkar |
| 2009 | VLSID | FPGA Based High Performance Double-Precision Matrix Multiplication. | Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan |
| 2009 | VLSID | Exploiting Hybrid Analysis in Solving Electrical Networks. | V. Siva Sankar, H. Narayanan, Sachin B. Patkar |
| 2003 | VLSID | An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. | Sachin B. Patkar, H. Narayanan |
| 1999 | PDPTA | Priority Scheduling in Parallel I/O Systems. | C. R. Venugopal, S. S. S. P. Rao, Sachin B. Patkar |
| 1997 | VLSID | A New Partitioning Strategy Based on Supermodular Functions. | Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan |
| 1994 | MFCS | Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach. | H. Narayanan, Subir K. Roy, Sachin B. Patkar |
| 1992 | ISAAC | Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity. | Sachin B. Patkar, H. Narayanan |