Saeideh Shirinzadeh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
8
Active years
2015–2026
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DDECS | Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing. | Saeideh Nabipour, Chandan Kumar Jha, Saeideh Shirinzadeh, Rolf Drechsler |
| 2026 | DDECS | Fan-In Aware Graph-Based Optimization for MAC-Based in-Memory Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | DSD | A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2024 | VLSID | In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. | Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler |
| 2023 | ASPDAC | Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. | Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler |
| 2022 | DSD | Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. | Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler |
| 2020 | ISCAS | Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. | Saman Frhlich, Saeideh Shirinzadeh, Rolf Drechsler |
| 2017 | DATE | Endurance management for resistive Logic-In-Memory computing architectures. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler |
| 2017 | GECCO | An adaptive prioritized | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | DAC | An MIG-based compiler for programmable logic-in-memory architectures. | Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Rolf Drechsler, Giovanni De Micheli |
| 2016 | DATE | Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| 2016 | DDECS | Multi-objective BDD optimization for RRAM based circuit design. | Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| 2016 | GECCO | Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2015 | GECCO | Multi-Objective BDD Optimization with Evolutionary Algorithms. | Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |